Welcome to the System Verilog tutorial series! If you have any doubts / suggestions, please let us know! 

What is System Verilog?


SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. SystemVerilog was created by the donation of the Superlog language to Accellera in 2002. The bulk of theverification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005.

Few of SystemVerilog’s capabilities are unique, but it is significant that these capabilities are combined and offered within a single HDL. There is great value in a common HDL which handles all aspects of the design and verification flow: design description, functional simulation, property specification, and formal verification.