Arrays in System Verilog

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Arrays hold a fixed number of equally-sized data elements. Individual elements are accessed by index using a consecutive range of integers. Some type of arrays allows to access individual elements using non consecutive values of any data types. Arrays can be classified as fixed-sized arrays (sometimes known as static arrays) whose size cannot change once their declaration is done, or dynamic arrays, which can be resized.

Fixed Arrays:

“Packed array” to refer to the dimensions declared before the object name and “unpacked array” refers to the dimensions declared after the object name.
SystemVerilog accepts a single number, as an alternative to a range, to specify the size of an unpacked array. That is, [size] becomes the same as [0:size-1].

int Array[8][32]; is the same as: int Array[0:7][0:31];

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// Packed Arrays
reg [0:10] vari; // packed array of 4-bits
wire [31:0] [1:0] vari; // 2-dimensional packed array
// Unpacked Arrays
wire status [31:0]; // 1 dimensional unpacked array
wire status [32]; // 1 dimensional unpacked array
integer matrix[7:0][0:31][15:0]; // 3-dimensional unpacked array of integers
integer matrix[8][32][16]; // 3-dimensional unpacked array of integers
reg [31:0] registers1 [0:255]; // unpacked array of 256 registers; each
reg [31:0] registers2 [256]; // register is packed 32 bit wide
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Operations On Arrays:

The following operations can be performed on all arrays, packed or unpacked:

register1 [6][7:0] = `1; // Packed indexes can be sliced
register1 = ~register1 ; // Can operate on entire memory
register1 = register2 ; // Reading and writing the entire array
register1[7:4] = register2[3:0] // Reading and writing a slice of the array
register1[4+:i]= register2[4+;i] // Reading and writing a variable slice
if(register1 == register2) //Equality operations on the entire array
int n[1:2][1:3] = `{`{0,1,2},`{4,4,3}};// multidimensional assignment
int triple [1:3] = `{1:1, default:0}; // indexes 2 and 3 assigned 0

Accessing Individual Elements Of Multidimensional Arrays:

In a list of multi dimensions, the rightmost one varies most rapidly than the left most one. Packed dimension varies more rapidly than an unpacked.

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In the following example, each dimension is having unique range and reading and writing to a element shows exactly which index corresponds to which dimension.

module index();
bit [1:5][10:16] foo [21:27][31:38];
initial
begin
foo[24][34][4][14] = 1;
$display(" foo[24][34][4][14] is %d ",foo[24][34][4][14] );
end
endmodule

The result of reading from an array with an out of the address bounds or if any bit in the address is X or Z shall return the default uninitialized value for the array element type.

As in Verilog, a comma-separated list of array declarations can be made. All arrays in the list shall have the same data type and the same packed array dimensions.

module array();
bit [1:5][10:16] foo1 [21:27][31:38],foo2 [31:27][33:38];
initial
begin
$display(" dimensions of foo1 is %d foo2 is
%d",$dimensions(foo1),$dimensions(foo2) );
$display(" reading with out of bound resulted %d",foo1[100][100][100][100]);
$display(" reading with index x resulted %d",foo1[33][1'bx]);
end
endmodule

RESULT:
dimensions of foo1 is 4 foo2 is 4
reading with out of bound resulted x
reading with index x resulted x
bit [3:4][5:6]Array [0:2];

  • Accessing “Array[2]” will access 4 elements Array[2][3][5],Array[2][3][6],Array[2][4][5] and Array[2][4][6].
  • Accessing “Array[1][3]” will access 2 elements Array[1][3][5] and Array[1][3][6].
  • Accessing “Array[0][3][6]” will access one element.
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