Comparison of Array in  System Verilog

Static Array:

  • Size should be known at compilation time.
  • Time require to access any element is less.
  • if not all elements used by the application, then memory is wasted.
  • Not good for sparse memory or when the size changes.
  • Good for contagious data.

Associativearray:

  • No need of size information at compile time.
  • Time require to access an element increases with size of the array.
  • Compact memory usage for sparse arrays.
  • User don’t need to keep track of size. It is automatically resized.
  • Good inbuilt methods for Manipulating and analyzing the content.

Dynamicarray:

  • No need of size information at compile time.
  • To set the size or resize, the size should be provided at runtime.
  • Performance to access elements is same as Static arrays.
  • Good for contagious data.
  • Memory usage is very good, as the size can be changed dynamically.

Queues:

  • No need of size information at compile time.
  • Performance to access elements is same as Static arrays.
  • User doesn’t need to provide size information to change the size. It is automatically resized.
  • Rich set of inbuilt methods for Manipulating and analyzing the content.
  • Useful in self-checking modules. Very easy to work with out of order transactions.
  • Inbuilt methods for sum of elements, sorting all the elements.
  • Searching for elements is very easy even with complex expressions.
  • Useful to model FIFO or LIFO.
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