Welcome to the System Verilog tutorial series! If you have any doubts / suggestions, please let us know!  Dear visitor, please Sign up / Login for Free and get privileged access! You can copy code, download free tutorials and do more when you’re logged in!

Data types in System Verilog

SystemVerilog adds extended and new data types to Verilog for better encapsulation and compactness. SystemVerilog extends Verilog by introducing C like data types.

SystemVerilog adds a new 2-state data types that can only have bits with 0 or 1 values unlike verilog 4-state data types which can have 0, 1, X and Z.SystemVerilog also allows user to define new data types.

SystemVerilog offers several data types, representing a hybrid of both Verilog and Cdata types. SystemVerilog 2-state data types can simulate faster, take less memory,and are preferred in some design styles. Then a 4-state value is automatically converted to a 2-state value, X and Z will be converted to zeros.


TIP: If you don’t need the x and z values then use the SystemVerilog int and bit types which make execution faster.

Signed And Unsigned:
Integer types use integer arithmetic and can be signed or unsigned.The data types byte, shortint, int, integer, and longint default to signed. The data types bit, reg, and logic default to unsigned, as do arrays of these types. To use these types as unsigned, user has to explicitly declare it as unsigned.

int unsigned ui;
int signed si
byte unsigned ubyte;

//User can cast using signed and unsigned casting.
if (signed'(ubyte)< 150) // ubyte is unsigned

The void data type represents nonexistent data. This type can be specified as the return type of functions to indicate no return value.

void = function_call();