Interface Methods

Welcome to the System Verilog tutorial series! If you have any doubts / suggestions, please let us know!  Dear visitor, please Sign up / Login for Free and get privileged access! You can copy code, download free tutorials and do more when you’re logged in!

Methods In Interfaces:

Interfaces can include task and function definitions. This allows a more abstract level of modeling.

interface intf (input clk);
logic read, enable,
logic [7:0] addr,data;
task masterRead(input logic [7:0] raddr); // masterRead method
...
endtask: masterRead
task slaveRead; // slaveRead method
...
endtask: slaveRead
endinterface :intf