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Literals  in System Verilog

Integer And Logic Literals:
In verilog , to assign a value to all the bits of vector, user has to specify them explicitly.

 reg[31:0] a = 32'hffffffff; 

System verilog Adds the ability to specify unsized literal single bit values with a preceding (‘).’0, ‘1, ‘X, ‘x, ‘Z, ‘z // sets all bits to this value.

reg[31:0] a = '1;
'x is equivalent to Verilog-2001 'bx
'z is equivalent to Verilog-2001 'bz
'1 is equivalent to making an assignment of all 1's
'0 is equivalent to making an assignment of 0

Array Literals:
Array literals are syntactically similar to C initializers, but with the replicate operator( {{}} ) allowed.

EXAMPLE:

int n[1:2][1:3] = '{'{0,1,2},'{3{4}}};

The nesting of braces must follow the number of dimensions, unlike in C. However, replicate operators can be nested. The inner pair of braces in a replication is removed. A replication expression only operates within one dimension.

EXAMPLE:

int n[1:2][1:6] = '{2{'{3{4, 5}}}}; // same as '{'{4,5,4,5,4,5},'{4,5,4,5,4,5}

Structure Literals:
Structure literals are structure assignment patterns or pattern expressions with constant member expressions A structure literal must have a type, which may be either explicitly indicated with a prefix or implicitly indicated by an assignment-like context.

EXAMPLE:

typedef struct {int a; shortreal b;} ab;
ab c;
c = '{0, 0.0}; // structure literal type determined from
// the left-hand context (c)

Nested braces should reflect the structure.

EXAMPLE:

ab abarr[1:0] = '{'{1, 1.0}, '{2, 2.0}};

The C-like alternative ‘{1, 1.0, 2, 2.0} for the preceding example is not allowed.

EXAMPLE: default values

c = '{a:0, b:0.0};
c = '{default:0};
d = ab'{int:1, shortreal:1.0};