Verilog procedural statements are in initial or always blocks, tasks, or functions. SystemVerilog adds a final block that executes at the end of simulation.SystemVerilog final blocks execute in an arbitrary but deterministic sequential order. This is possible because final blocks are limited to the legal set of statements allowed for functions.
$display(" END OF SIMULATION at %d ",$time);
END OF SIMULATION at 100
SystemVerilog has statements to control the loop statements.
- break : to go out of loop as C
- continue : skip to end of loop as C
- return expression : exit from a function
- return : exit from a task or void function
Any change in a variable or net can be detected using the @ event control, as in Verilog. If the expression evaluates to a result of more than 1 bit, a change on any of the bits of the result (including an x to z change) shall trigger the event control.
SystemVerilog adds an iff qualifier to the @ event control.
module latch (output logic [31:0] y, input [31:0] a, input enable);
always @(a iff enable == 1)
y <= a; //latch is in transparent mode
In an always block that is used to model combinational logic, forgetting an else leads to an unintended latch. To avoid this mistake, SystemVerilog adds specialized always_comb and always_latch blocks, which indicate design intent to simulation, synthesis, and formal verification tools. SystemVerilog also adds an always_ff block to indicate sequential logic.
a = b & c;
if(ck) q <= d;
always_ff @(posedge clock iff reset == 0 or posedge reset)
r1 <= reset ? 0 : r2 + 1;