SV TestBench and Verilog DUT

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Working With Verilog Dut:

There are several ways to connect the Verilog DUT to SystemVerilog TestBench. Verilog DUT has port list where as SystemVerilog testbenchs uses interfaces. We will discuss 2 ways of connecting Verilog DUT to SystemVerilog TestBench.

Connecting In Top:

Verilog port list can be connected during DUT instantiation using interface hibachi signal names as shown in following code.

// DUT in Verilog
module Dut (input clk, read, enable,
Input [7:0] addr,
output [7:0] data);
....
assign data = temp1 ? temp2 : temp3 ;
always @(posedge clk)
....
endmodule
// SystemVerilog Code
// interface declaration with clocking block:
interface intf (input clk);
logic read, enable,
logic [7:0] addr,data;
endinterface
module testbench(intf.tb tb_if);
.....
endmodule
// integrating in top module.
module top();
logic clk;
intf bus_if(clk); // interface instantiation
Testbench TB (bus_if); // Pass the modport into the module
Dut d(.clk(clk), // connect the verilog
.read(bus_if.read), // RTL port using interface hierarchy signal name.
.enable(bus_if.enable),
.addr(bus_if.addr),
.data(bus_if.data);
endmodule

Connecting Using A Wrapper:

We can also convert the verilog module with port list in to SystemVerilog module with interface by creating wrapper around the verilog module.

//wrapper for verilog DUT
module w_dut(intf wif);
Dut d(.clk(wif.clk), // connect the verilog
.read(wif.read), // RTL port using interface hierarchy signal name.
.enable(wif.enable),
.addr(wif.addr),
.data(wif.data);
endmodule
//connecting the dut wrapper and testbench in top.
module top();
logic clk;
intf bus_if(clk); // interface instantiation
w_dut d(bus_if); // instance of dut wrapper
Testbench TB (Bus_if);
endmodule