TypeDEF in System Verilog

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A typedef declaration lets you define your own identifiers that can be used in place of type specifiers such as int, byte, real. Let us see an example of creating data type “nibble”.

typedef bit[3:0] nibble; // Defining nibble data type.
nibble a, b; // a and b are variables with nibble data types.

Advantages Of Using Typedef:

  1. Shorter names are easier to type and reduce typing errors.
  2. Improves readability by shortening complex declarations.
  3. Improves understanding by clarifying the meaning of data.
  4. Changing a data type in one place is easier than changing all of its uses throughout the code.
  5. Allows defining new data types using structs, unions and Enumerations also.
  6. Increases reusability.
  7. Useful is type casting.

Example: of typedef using struct, union and enum data types.

typedef enum {NO, YES} boolean;
typedef union { int i; shortreal f; } num; // named union type
typedef struct {
bit isfloat;
union { int i; shortreal f; } n; // anonymous type
} tagged_st; // named structure
boolean myvar; // Enum type variable
num n; // Union type variable
tagged_st a[9:0]; // array of structures